If the computer system is in a compute intensive or network intensive environment that requires high throughput, the memory bandwidth will also be an important memory consideration in addition to the size of the memory.
Memory bandwidth is primarily determined by the speed of the memory controller (chipset), DRAM device technology and system design. Today, it is measured in GB/sec and calculated by multiplying the bus width by and the data rate. For example, a DDR2-400 (PC-3200) memory subsystem in a dual channel system configuration, would have a memory bandwidth of 6.4GB/sec (128 bit bus width (two 64bit memory buses) x 400Mbps data rate x 1byte/8bits = 6400MB/sec).
Memory bandwidth is often impacted by the "speed/density" equation where speed and density can have an inverse relationship. The more DRAM devices that are added to the memory bus to increase system memory, the higher the capacitive loading on the Data-Address-Control (DAC) bus which degrades signal quality at higher speeds.
RAMpedia is a DRAM memory encyclopedia and reference tool
to help computer hardware board designers with DRAM memory subsystems.
This information is provided as a courtesy by Virtium Technology. www.virtium.com