what is Parity - Parity checking is generated on the address and control bus of a RDIMM to report bus errors to the memory controller (or MCH). The memory channel will report that an error has occurred but it will not correct the error or stop the errors from occurring.

RAMpedia is a DRAM memory encyclopedia and reference tool
to help computer hardware board designers with DRAM memory subsystems.
This information is provided as a courtesy by Virtium Technology.
www.virtium.com