Getting Started with a Simulation Report
1) Ask Virtium to run a memory subsystem level IBIS simulation and prepare a report predicting system level noise, timing margins and signal integrity characteristics.
The Report will contain the following items:
a) Recommended Topology Diagrams
DIMM Clocking
Address/Command signal group
Control signal group
Data signal group
Data Strobes
b) Eye-Diagrams showing values for jitter and slew rates
PLL Clock group
PLL/Register group
Address/Command signal group
Control signal group
Data signal group
Data strobes
c) System timing margin showing
Setup/hold values
Rmin Etch Delay
Rmax Etch Delay
Fmin Etch Delay
Fmax Etch Delay
2) Virtium will get the IBIS Models for chipset/memory controller hub and DRAM and motherboard design. This may require a 3-way NDA with memory controller (chipset) vendor, memory module vendor and the maker of the system motherboard.
3) The are several simulation tools are available, such as SiSoft, and Cadenace Spectraquest, but Virtium prefers the SiSoft tool, since it was designed with special features for memory simulations. If you have a preference, please specify what type of simulation you want conducted on your system and memory:
a) Pulse
b) Rising Edge
c) Sinewave
d) Pulse Eye
e) Falling Edge
f) Crosstalk
RAMpedia is a DRAM memory encyclopedia and reference tool
to help computer hardware board designers with DRAM memory subsystems.
This information is provided as a courtesy by Virtium Technology.
www.virtium.com
